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"FPGAs for Signal Processing and Embedded Application" Seminar at MS   Message List  
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"FPGAs for Signal Processing and Embedded Application" Seminar at MSRSAS from 4th to 5th March 2010.


Dear Sir / Madam,

 

Sub: Three Day Seminar on "FPGAs for Signal Processing and Embedded Application"  

 

M. S. Ramaiah School of Advanced Studies (MSRSAS) is organizing a three day seminar on “FPGAs for Signal Processing and Embedded Application” on 4th, 5th & 6th

March 2010. The seminar information is given below for your kind reference. The contents will be extremely beneficial to the practicing engineers, professionals, academic staff and students. It is requested to kindly circulate the Seminar information among your staff and kindly consider nominating few staff members / students from your organization / institution / division / group to register and attend this three day seminar.   We do hope that the Seminar will provide a valuable forum for interaction with the domain experts, helping the participants in their professional growth.

 

Thanking you and with warm regards,

 

S.Vijaykumar 
Manager - Academic Relations 
____________________________________________________
M.S.Ramaiah School of Advanced Studies (MSRSAS)
Gnanagangothri Campus, New BEL Road, MSR Nagar
Bangalore : 560 054
Tel No. : +91 80 2360 5539 / 2360 1983 / 2360 4759

Fax No. : +91 80 2360 1923

Direct No: +91 80 4167 4719

Mobile No: +91 9886394532

Email: vijaykumar@...; vijay.msrsas@...

Group ID: http://groups.yahoo.com/groups/MSRSAS_CPD

Website: www.msrsas.org / www.msrsas.org/Training&LifeLongLearning/seminars.htm.

 

------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Three Day Seminar on 

" FPGAs for Signal Processing and Embedded Application"

Organized by

M. S. Ramaiah School of Advanced Studies

Date: 4th, 5th & 6th March 2010
(Thursday, Friday & Saturday)

Venue: M. S. Ramaiah School of Advanced Studies, Bangalore

 

Overview:

 

Field Programmable Gate Arrays (FPGAs) are finding prominence in many applications such as complex signal processing, communication, networking and control systems. FPGAs have surpassed the ASICs by increasing gate counts by more than three orders of magnitude since their inception about two decades ago. Also, they have added high-speed I/Os, embedded memories, dedicated Phase-Locked Loops (PLLs), and embedded processors. An important aspect of FPGAs is the availability of pre-designed circuit blocks in the form of Intellectual Property (IP) that designers can license and integrate into their system. FPGA based system design is finding its place in many fields such as medical, automotive, industrial, commercial and military. FPGAs support reconfigurability of complex digital designs, multicore processors, DSP and communication block sets along with debugging capabilities. However, many of the current designs get implemented on microcontrollers and ASICs. One of the reasons for this is the lack of awareness and ease of working with the FPGA software and hardware tools. In order to exploit the capabilities of FPGAs and to develop complex applications with reduced time, it is required to understand and practice the correct methodology and follow the guidelines while working with FPGAs. Engineers need to know the shortcuts and industry practices for successfully designing applications using FPGAs. Also it is required to understand the software solutions and tools available for designing and debugging FPGAs. There is a frequent need to develop customized boards using FPGAs. This seminar is one such event which introduces and demonstrates the best practices of FPGA in industry.

                                                     

Objectives:

 

• To discuss the challenges and opportunities in FPGA based system design

• To understand the basic/advanced FPGA architecture and FPGA design flow

• To design complex systems using FPGAs without HDLs and Implement the design with area   

   and timing optimization on FPGA

• To design, implement and debug signal processing and embedded applications on FPGAs

• To understand the challenges and solution procedures in developing FPGA based High Speed

   Boards

 

Who should attend?

 

Experienced Engineers, working professionals, faculties, students (M.Tech. /B.E. / Diploma) and fresher

 

Prerequisites

 

Participants need to have basic understanding of digital circuits, HDLs, signal processing and embedded systems

 

Program Schedule

 

Day 1: 04.03.2010                              Designing with FPGAs

 

Session

 

Time

 

Topics

 

Faculty

I

9.00 AM – 9.30 AM

Registration

 

II

9.30 AM – 10.30 AM

Key Note Address

Experts from Xilinx

Tea / Coffee Break

II

10.45 AM - 12.00 PM

FPGA Architecture - Basic and Advanced

Mr. Cyril Prasanna Raj.P

MSRSAS,

III

12.00 PM – 1.00 PM

FPGA Design Flow

Mr. Cyril Prasanna Raj.P

MSRSAS

Lunch Break

III

2.00 PM –3:30 PM

FPGA Synthesis and Industry Practices

Mr. Selva Kumar

MSRSAS

Tea / Coffee Break

IV

3:45 PM – 5.30 PM

IP Cores and Timing Analysis

Mr. Vasudeva Murthy

MSRSAS

 

Day 2: 05.03.2010                       FPGAs for Signal Processing

 

Session

 

Time

 

 

Topics

 

 

Faculty

 

I

9.30 AM – 11.15 AM

FPGAs for Signal Processing

Experts from Industry

Tea / Coffee Break

II

11.30 AM - 1.00 PM

Digital Down/Up Converters

Image processing using FPGAs

Mr. Cyril Prasanna Raj.P

MSRSAS

Lunch Break

III

2.00 PM – 3.30 PM

FPGAs and Signal Processing

[Hardware/Software Interface] - DEMO

Mr. Cyril Prasanna Raj.P

MSRSAS

Tea / Coffee Break

IV

3.45 PM– 5.30 PM

FPGA for Quicker Designs

[Plan Ahead, Lab View]

Mr. Selva Kumar

MSRSAS

           

Day 3: 06.03.2010                       FPGAs for Embedded Applications

Session

 

 

Time

 

 

Topics

 

 

Faculty

 

I

9.30 AM – 11.15 AM

FPGAs for Embedded System

Experts from Industry

Tea / Coffee Break

II

11.30 AM - 1.00 PM

 Microcontrollers and OS on FPGA

Mr. Padmanabhan

MSRSAS

Lunch Break

III

2.00 PM – 3.30 PM

Embedded Development Cycle using FPGAs

[Implementation and DEMO]

Mr. Padmanabhan

MSRSAS

Tea / Coffee Break

IV

3.45 PM– 5.30 PM

FPGA Board Design

[System Development]

Mr. Martin

MSRSAS

 

For technical queries please contact:

Mr. Cyril Prasanna Raj P.
Asst. Professor & CM (VSD), MSRSAS,

E-mail: cyril@... / cyrilyahoo@...
Phone: 080- 2360 5539/1983/4759

Cell: 9448686332 / 9916293433

 

Please send your registration to,

Mr. Vijaykumar S.
Manager - Academic Relations
E-Mail: vijaykumar@...vijay.msrsas@...
Mobile : 98863 94532

Ms. Archana Madhukar
Executive- Academic Relations
E-mail: archana.m@... , archanamsrsas@...

Mobile: 9686447343 / 9986642719

 

Ms. Roopa V.
Asst. Executive- Academic Relations
E-mail: roopa@..., rupamsrsas@...
Mobile : 96630 63832

 

Phone: 080-2360 5539 / 1983 / 4759, Fax: 080 - 2360 1923    Direct: 4167 4719

Last date for registration – 2nd March 2010
Note: Outstation participants to send only DD/at par cheque

Registration Fee:

Rs. 3,500/- For Industrial Participants
Rs. 3,000/- For Participants from Govt. Research Organisations
Rs. 2,000/- For Faculty from Academic Institutions
Rs. 1,000/- For Students from Academic Institutions
(Inclusive of course material, lunch & tea)

Note: Payments to be made through D.D. in favour of:  M. S. Ramaiah School of Advanced Studies, Payable at Bangalore . 

REGISTRATION FORM

M.S.RAMAIAH SCHOOL OF ADVANCED STUDIES
Gnanagangothri Campus,
New BEL Road , M.S.R Nagar,
Bangalore – 560 054, INDIA .
Telefax: 91-80-2360 5539, 2360 1983, 2360 4759
e-mail : cpd@...
Website: www.msrsas.org

 Programme : “FPGAs for Signal Processing and Embedded Application”

Date: 4th, 5th & 6th March 2010 (Thursday, Friday & Saturday)

Please register the following nominations

Name Designation

1)______________________________________________

2)______________________________________________

3)______________________________________________

4)______________________________________________

5)______________________________________________

We enclose Cheque / DD No:____________ dated_________for Rs._________ drawn in favour of M.S.Ramaiah School of Advanced Studies, Payable at Bangalore .

 

Nominated By

Name: _________________________________________

Designation: ____________________________________

Organization ____________________________________

Address: _______________________________________

_______________________________________________

_______________________________________________

Phone Nos:_______________________________________

Fax Nos:_________________________________________

E-Mail: __________________________________________

 

Signature with Seal
Date:

 

 

 



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Wed Feb 10, 2010 10:55 am

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Dear Sir / Madam, Sub: Three Day Seminar on "FPGAs for Signal Processing and Embedded Application" M.S. Ramaiah Schoolof Advanced Studies (MSRSAS) is...
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